Wafer-level testing is a critical process to ensure that integrated circuits and semiconductor devices properly function. That is, wafer-level testing can be used to determine the characteristics or functionality of the integrated circuits and semiconductor devices. The integrated circuits and semiconductor devices that are being tested are typically referred to as device(s) under test (DUT).
Wafer-level testing is performed on a probe card assembly of a wafer prober. During integrated circuit wafer level test, individual integrated circuit chips, e.g., DUTs, are tested by temporarily contacting individual power and signal I/O connections, such as solder bumps, with probes mounted to a probe card assembly of a tester. However, as the number and density of I/Os increase it becomes increasingly difficult to ensure uniform and low resistance contact between the probes and each I/O connection. The probe card assembly plays a significant role in ensuring this contact.